1. Field of the Invention
The present invention relates to a solid-state image pickup apparatus and a solid-state image pickup method.
Priority is claimed on Japanese Patent Application No. 2008-278293 filed on Oct. 29, 2008, the contents of which are incorporated herein by reference.
2. Description of Related Art
An image pickup apparatus (for example, a digital still camera) which converts an optical signal to an electric signal and outputs an image signal is known. As a solid-state image pickup apparatus which is used for an image pickup device of the image pickup apparatus, a lot of research and development relating to a MOS (Metal-Oxide Semiconductor) type solid-state image pickup apparatus has been conducted.
FIG. 15 is a circuit diagram showing a conventional MOS type solid-state image pickup apparatus which is able to switch between a first mode, which thins out and reads out pixels, and a second mode, which reads out all pixels (for example, Japanese Unexamined Patent Publication, First Publication No. H11-191891). The MOS type solid-state image pickup apparatus includes a vertical scanning section 2, vertical signal lines 3_1 to 3_4, column circuits 4_1 to 4_4 and pixels 11 to 24.
The vertical scanning section 2 supplies a pulse for reading out electric signal to the pixels 11 to 14 and pixels 21 to 24 which are arranged in a matrix. The vertical signal lines 3_1 to 3_4 transmit signals which are outputted from pixels 11 to 24. The column circuits 4_1 to 4_4 perform analog processing for signals of the vertical signal lines 3_1 to 3_4.
The MOS type solid-state image pickup apparatus includes a horizontal scanning section 5, horizontal signal lines 6_1 and 6_2, output amplifiers 7_1 and 7_2, a mode setting section 8 and a column selection transistor M9. The column selection transistor M9 selectively outputs signals from the column circuits 4_1 to 4_4 to the horizontal signal lines 6_1 and 6_2. The horizontal scanning section 5 supplies a pulse for selecting column to the column selection transistor M9. The output amplifiers 7_1 and 7_2 amplify and output signals outputted from the horizontal signal lines 6_1 and 6_2. The mode setting section 8 switches a plurality of modes for reading out electric signal.
In aforementioned solid-state image pickup apparatus, in case of a mode which reads out all pixels, the signals which are outputted from the column circuits 4_1 to 4_4 are read out to the horizontal signal lines 6_1 and 6_2 by column selection pulses φH1 to φH4. The output amplifiers 7_1 and 7_2 output signals outputted from output channels OUT1 and OUT2.
In case of a mode for thinning out half column and reading out electric signal, the signals which outputted from the column circuits 4_1 and 4_3 are read out to the horizontal signal line 6_1 by column selection pulses φH1 and φH3. Then, the output amplifier 7_1 reads out a signal of the output channel OUT1, and does not read out from the column circuits 4_2 and 4_4. In this case, the mode setting section 8 reduces the bias current of the output amplifier 7_2 which is not used. Therefore, whole electrical power consumption is reduced.
Recently, as a column circuit, a MOS type solid-state image pickup apparatus which has an amplification function has been developed. The conventional art shown in FIG. 15 which is applied to the column amplification function is described below, with reference to FIGS. 16 to 18. FIG. 16 is a circuit diagram showing a configuration of the conventional MOS type solid-state image pickup apparatus which is applied to the amplification function.
The MOS type solid-state image pickup apparatus includes a vertical scanning section 2, vertical signal lines 3_1 to 3_4, pixels 11 to 24, and a pixel bias current source IPIX. The vertical scanning section 2 supplies pulses for reading out electric signal to the pixels 11 to 14 and the pixels 21 to 24 which are arranged in a matrix. The vertical signal lines 3_1 to 3_4 transmit signals which are outputted from the pixels 11 to 24. The pixel bias current source IPIX flows a constant current to the vertical signal lines 3_1 to 3_4. In addition, the MOS type solid-state image pickup apparatus includes column circuits 4_1 to 4_4, a horizontal scanning section 5 and a column selection transistor M9. The column circuits 4_1 to 4_4 amplify and store electric potentials of the vertical signal lines 3_1 to 3_4. The column selection transistor M9 selectively outputs signals from the column circuits 4_1 to 4_4 to the horizontal signal lines 6_1 and 6_2. The horizontal scanning section 5 supplies a column selection pulse to the column selection transistor M9. In addition, the MOS type solid-state image pickup apparatus includes output amplifiers 7_1 and 7_2, a mode setting section 8 and a horizontal signal line reset transistor M10. The horizontal signal line reset transistor M10 resets horizontal signal lines 6_1 and 6_2 by a horizontal signal line reset voltage VR. The output amplifiers 7_1 and 7_2 amplify and output signals from the horizontal signal lines 6_1 and 6_2. The mode setting section 8 switches a plurality of modes for reading out.
The pixels 11 to 24 each include a photo diode PD, a transmission transistor M1, an amplification transistor M3, a reset transistor M2 and a row selection transistor M4. The photo diode PD converts an input optical signal to an electric signal. The transmission transistor M1 transmits the electric signal stored in the photo diode PD. The amplification transistor M3 amplifies a transmitted electric signal. The reset transistor M2 resets the electric potential of an electrode (for example, the gate electrode of the amplification transistor M3). The row selection transistor M4 selectively outputs the amplified signal based on the electric signal.
The vertical scanning section 2 supplies transmission pulses φTX1 and φTX2, reset pulses φRST1 and φRST2 and row selection pulses φROW1 and φROW2 to gates of the transmission transistor M1, the reset transistor M2 and the row selection transistor M4 row by row. The drain electrodes of the reset transistor M2 and the amplification transistor M3 are connected to the pixel electric source VDD.
The column circuits 4_1 to 4_4 include a column amplifier 41, a clamp capacity Cc and a clamp transistor M6. The column amplifier 41 amplifies the signals from the pixels 11 to 24. The clamp capacity Cc is connected to a non-inversion input terminal of the column amplifier 41, and clamps an output signal from the pixels 11 to 24 with a clamp voltage VC. The clamp transistor M6 supplies clamp voltage VC to the non-inversion input terminal of the column amplifier 41.
The column circuits 4_1 to 4_4 include a feedback capacity Cf, an amplification capacity Cg, a sample hold capacity Cs, an amplifier reset transistor M7 and a sample hold transistor M8. The feedback capacity Cf and the amplifier reset transistor M7 are connected between the non-inversion input terminal of the column amplifier 41 and an output terminal. The amplification capacity Cg is connected between the non-inversion input terminal of the column amplifier 41 and the ground, and sets the amplification factor of the column amplifier 41. The sample hold capacity Cs stores the output signal of the column amplifier 41. The sample hold transistor M8 connects the output terminal of the column amplifier 41 and the sample hold capacity Cs.
A column circuit bias current control voltage VBIAS for controlling the bias current of the column amplifier 41 is supplied to the column circuits 4_1 to 4_4. The clamp pulse φCL is inputted to the gates of the clamp transistor M6 and the amplifier reset transistor M7. The sample hold pulse φHS is inputted to the gate of the sample hold transistor M8.
The column selection pulses φH1 to φH4 are inputted to each of the gates of the column selection transistor M9. The horizontal signal line reset pulse φRS is inputted to the gate of the horizontal signal line reset transistor M10.
Next, an operation of the MOS type solid-state image pickup apparatus shown in FIG. 16 is described below with reference to timing charts of FIGS. 17 and 18. In addition, in voltage level, a high level is indicated with the character “H”, and a low level is indicated with the character “L”.
FIG. 17 is a timing chart showing an operation for reading out all pixels in the MOS type solid-state image pickup apparatus. First, an operation for reading out from the pixels 11 to 14 of the first row is enabled by the vertical scanning section 2.
Next, the vertical scanning section 2 sets the row selection transistor M4 to an ON-state by setting row selection pulse φROW1 to “H”, and reads out the output of the amplification transistor M3 to each of the vertical signal lines 3_1 to 3_4.
Next, the vertical scanning section 2 sets the reset transistor M2 to the ON-state by setting reset pulse φRST1 to “H”, and resets the gate of the amplification transistor M3 to the reset electric potential. Next, the vertical scanning section 2 reads out the output signals in response to the reset voltage of the pixels 11 to 14. Here, the vertical scanning section 2 sets the clamp pulse φCL to “H”, and resets the column circuits 4_1 to 4_4 by setting the amplifier reset transistor M7 to the ON-state. In addition, the vertical scanning section 2 clamps the non-inversion input terminal of the column amplifier 41 to the clamp voltage VC by setting the clamp transistor M6 to the ON-state.
Next, the vertical scanning section 2 sets the reset pulse φRST1 to “L”, and sets the clamp pulse φCL to “L”, and finishes a clamp processing. Next, the vertical scanning section 2 sets the transmission pulse φTX1 to “H”, and sets the transmission transistor M1 to the ON-state. In addition, the vertical scanning section 2 transmits the electric signal involved in the optical signal which occurred in the photo diode PD to the gate of the amplification transistor M3, and sets the transmission pulse φTX1 to “L”. Therefore, the amplified electric signals involved in optical signals of each pixels are outputted to each of the vertical signal lines 3_1 to 3_4.
In addition, the non-inversion input terminal of the column amplifier 41 changes, by the clamp capacity Cc, a variation ΔSig based on the electric signal involved in the optical signal from the reset electric potential of the pixels 11 to 14. Here, the output of the column amplifier 41 changes (1+Cg/Cf)ΔSig compared to the clamp voltage VC. In addition, the sample hold pulse is set to “H” (φHS=“H”), and the signal read out from the column amplifier 41 is read out to the sample hold capacity Cs, and the signal is stored as the sample hold pulse φHS (φHS=“L”).
Finally, the horizontal signal lines 6_1 and 6_2 are reset to the horizontal signal line reset voltage VR by the horizontal signal line reset pulse φRS. In addition, the output signals which stored in the sample hold capacity Cs are read out to the horizontal signal lines 6_1 and 6_2 by the column selection pulses φH1 and φH2. Then, the horizontal signal lines 6_1 and 6_2 are reset to the horizontal signal line reset voltage VR by the horizontal signal reset pulse φRS. Then, the output signals of the column circuits 4_3 and 4_4 stored in the sample hold capacity Cs are read out to the horizontal signal lines 6_1 and 6_2 by the column selection pulses φH3 and φH4.
Aforementioned operations are repeated. Then, the signal from the column circuits are read out to the horizontal signal lines 6_1 and 6_2 sequentially, and are outputted to the output channels OUT1 and OUT2 via the output amplifiers 7_1 and 7_2. After the signals in one row are all read out, the signals in next row are read out.
Next, an operation of a ½ column thinning out mode that is thinning out and reading out electric signals of the each column circuits 4_1 to 4_4 is described with reference to FIG. 18. The operation for reading out the pixel signals and processing of the column circuits is similar to the mode for reading out all pixels shown in FIG. 17. Here, the operation for reading out the amplified pixel signals, which are stored in the sample hold capacity Cs and supplying the signals to the horizontal signal line 6_1 is described.
First, the horizontal signal lines 6_1 and 6_2 are reset to the horizontal signal line reset voltage VR by the horizontal signal line reset pulse φRS. Next, the column selection pulse φH1 is set to “H” (φH1=“H”), and the signal of the column circuit 4_1 is read out to the horizontal signal line 6_1, and the signal of the column circuit 4_2 is not read out. Next, the horizontal signal lines 6_1 and 6_2 are reset to the horizontal signal line reset voltage VR by the horizontal signal line reset pulse φRS. Then, the column selection pulse φH3 is set to “H” (φH3=“H”), and the signal of the column circuit 4_3 is read out to the horizontal signal line 6_1, and the signal of the column circuit 4_4 is not read out.
This operation is repeated, and the signals of the column circuits are thinned out and read out to the horizontal signal line 6_1 sequentially, the signal of the output channel OUT1 is only read out using the output amplifier 7_1. When all signals of the one column are read out, the signals of the next column are read out similarly. Here, the bias current of the output amplifier 7_2 which is not used is reduced by the mode setting section 8.
The electric signal ΔSig from the column circuits 4_1 to 4_4 is increased by (1+Cg/Cf) times. Therefore, the noises occurred after column circuits 4_1 to 4_4 are reduced, and it is possible to obtain good quality images. In addition, in the mode for thinning out the electric signal of the columns, it is possible to reduce the consumption of electric power by reducing the bias current of the output amplifier which is not used.